![]() ![]() Heterogeneous integration of atomically thin semiconductors for non-von Neumann CMOS. A microprocessor based on a two-dimensional semiconductor. Robotic four-dimensional pixel assembly of van der Waals solids. Ballistic two-dimensional InSe transistors. Ultra-scaled MOCVD MoS 2 MOSFETs with 42 nm contact pitch and 250 ♚/µm drain current. Approaching the quantum limit in two-dimensional semiconductor contacts. Ultralow contact resistance between semimetal and monolayer semiconductors. Step engineering for nucleation and domain orientation control in WSe 2 epitaxy on c-plane sapphire. Batch production of 6-inch uniform monolayer molybdenum disulfide catalyzed by sodium in glass. Non-epitaxial single-crystal 2D material growth by geometric confinement. Uniform nucleation and epitaxy of bilayer molybdenum disulfide on sapphire. Promises and prospects of two-dimensional transistors. Scaling challenges for advanced CMOS devices. High Mobility Materials for CMOS Applications (Elsevier, 2018). 2019 on Great Lakes Symposium on VLSI 439–444 (ACM, 2019).Ĭollaert, N. An overview of thermal challenges and opportunities for monolithic 3D ICs. An in-memory computing architecture based on a duplex two-dimensional material structure for in situ machine learning. ![]() Hybrid 2D–CMOS microchips for memristive applications. Transistors based on two-dimensional materials for future integrated circuits. In 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) 1103–1107 (IEEE, 2022).Ĭao, W. 3D packaging for heterogeneous integration. TSMC packaging technologies for chiplets and 3D. Foveros: 3D integration and the use of face-to-face chip stacking for logic devices. Graphene and two-dimensional materials for silicon technology. 3D-stacked CMOS takes Moore’s law to new heights. We believe that our demonstrations will serve as the foundation for more sophisticated, highly dense and functionally divergent integrated circuits with a larger number of tiers integrated monolithically in the third dimension. We also realize a 3D circuit and demonstrate multifunctional capabilities, including sensing and storage. Here we demonstrate (1) wafer-scale and monolithic two-tier 3D integration based on MoS 2 with more than 10,000 field-effect transistors (FETs) in each tier (2) three-tier 3D integration based on both MoS 2 and WSe 2 with about 500 FETs in each tier and (3) two-tier 3D integration based on 200 scaled MoS 2 FETs (channel length, L CH = 45 nm) in each tier. Although silicon-based 3D integrated circuits are commercially available 3, 4, 5, there is limited effort on 3D integration of emerging nanomaterials 6, 7 such as two-dimensional (2D) materials despite their unique functionalities 7, 8, 9, 10. In the field of semiconductors, three-dimensional (3D) integration not only enables packaging of more devices per unit area, referred to as ‘More Moore’ 1 but also introduces multifunctionalities for ‘More than Moore’ 2 technologies. ![]()
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